1. Technical Field
The present invention relates to digital circuits in general, and, in particular, to fused multiply-adder circuits. Still more particularly, the present invention relates to a three-path fused multiply-adder circuit.
2. Description of Related Art
A floating-point unit is designed to perform various mathematical operations on floating-point numbers. It is always useful to enhance the speed of a floating-point unit, and one known technique is to provide specialized hardware to implement certain floating-point functions. For example, a fused multiply-adder circuit can be implemented within a floating-point unit to perform multiply-accumulate functions that are commonly used in digital signal processing operations.
A fused multiply-adder circuit basically combines a multiplication operation with an add operation to perform a single instruction execution of the equation (A×B)+C. Within a fused multiply-adder circuit, a multiplicand and a multiplier are initially multiplied via a partial product generation module. The partial products are then added by a partial product reduction module that reduces the partial products to a Sum and a Carry in their redundant form. The redundant Sum and Carry are further added to an addend via a carry-save adder to form a second redundant Sum and a second redundant Carry. The second redundant Sum and the second redundant Carry are subsequently added within a carry-propagate adder to yield a Sum Total.
Since the early 1990s, a plethora of algorithms that utilize the (A×B)+C single-instruction equation have been introduced for applications in digital signal processing and graphics processing. To complement the ever increasing usage of the fused multiply-add instruction, the floating-point adder (FPA) and floating-point multiplier (FPM) of some chips are entirely replaced with a fused multiply-adder by using constants, such as (A×B)+0.0 for single multiplies and (A×1.0)+C for single adds. The combination of industrial implementation and increasing algorithmic activities has prompted the IEEE 754R committee to consider the inclusion of the fused multiply-add instruction into the IEEE standard for floating-point arithmetic.